A 3D Processor is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The semiconductor industry is pursuing this promising technology in many different forms, but it is not yet widely used. 3D packaging saves space by stacking separate chips in a single package. This packaging, known as System in Package (SiP) or Chip Stack MCM, does not integrate the chips into a single circuit.
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory. Due to the high demand for memory bandwidth, a traditional IO approach would consume 10 to 25W. To improve upon that, Intel designers implemented a TSV-based memory bus. Each core is connected to one memory tile in the SRAM die with a link that provides 12 GB/s bandwidth, resulting in a total bandwidth of 1 TB/s while consuming only 2.2W.
Note that these parts aren’t merely RAM-stacked-on-top-of-a-processor packages such as, for example, Apple’s A5. These are single parts with processor and memory closely coupled, married together in a single slab.